1. Field
The present embodiments relate, generally, to liquid crystal display devices, and more particularly, to a liquid crystal display device configured for lowering a generated heat temperature of a data integrated circuit and reducing power consumption, and a driving method thereof.
2. Description of the Related Art
A liquid crystal display device controls a light transmittance of liquid crystal cells in accordance with a video signal, thereby displaying a picture.
An active matrix type liquid crystal display device can actively control a switching device, thereby advantageously realizing a motion picture. A thin film transistor (hereinafter, referred to as “TFT”) is typically used as a switching device in the active matrix type liquid crystal display device.
Referring to FIG. 1, the liquid crystal display device includes a liquid crystal display panel 2 where a plurality of data lines 5 and a plurality of gate lines 6 cross each other and TFT's (not shown) are respectively formed at the crossing parts thereof for driving liquid crystal cells; a data driver 3 for supplying data to the data lines 5; a gate driver 4 for supplying scan pulses to the gate lines 6; and a timing controller 1 for controlling the data driver 3 and the gate driver 4.
The liquid crystal display panel 2 has a liquid crystal injected between two glass substrates (not shown), and has data lines 5 and gate lines 6 cross each other on the lower of the two glass substrate. A TFT formed at a crossing part of a corresponding data line 5 and a corresponding gate line 6 supplies a data signal from the data line 5 to a liquid crystal cell in response to a scan pulse from the gate line 6. As such, a gate electrode (not shown) of the TFT is connected to the gate line 6, and a source electrode (not shown) is connected to the data line 5. Moreover, a drain electrode (not shown) of the TFT is connected to a pixel electrode of the liquid crystal cell Clc. Further, a storage capacitor Cst (not shown) is formed on the lower glass substrate of the liquid crystal display panel 2 for sustaining a voltage of the liquid crystal cell.
The timing controller 1 receives a digital video data signal RGB from a system or unit (not shown), a horizontal synchronization signal (H), a vertical synchronization signal (V) and a clock signal CLK to generate a gate control signal GDC for controlling the gate driver 4 and to generate a data control signal DDC for controlling the data driver 3. Further, the timing controller 1 supplies the received data RGB signal to the data driver 3. The data control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, and a source output enable signal SOE to be supplied to the data driver 3. The gate control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, and a gate output enable GOE to be supplied to the gate driver 4.
The gate driver 4 includes a shift register which sequentially generates a scan pulse in response to the gate control signal GDC from the timing controller 1; a level shifter for shifting a swing width of the scan pulse to a level which is suitable for driving the liquid crystal cell Clc; and an output buffer. The gate driver 4 supplies the scan pulse to the gate line 6 to turn on (control) the TFT connected to the gate line 6, thereby selecting liquid crystal cells Clc of one horizontal line to which a pixel voltage of data, i.e., an analog gamma compensation voltage, is to be supplied. The data generated from the data driver 3 are supplied to the liquid crystal cells Clc of the horizontal line which is selected by the scan pulse.
The data driver 3 supplies the data to the data lines 5 in response to the data drive control signal DDC supplied from the timing controller 1. The data driver 3 samples the digital data RGB from the timing controller 1, latches the data, and then converts the data into an analog gamma voltage. The data driver 3 comprises a plurality of data integrated circuits (hereinafter, referred to as “IC”) 3A having a configuration as shown in FIG. 2.
Each of the data IC's 3A, as shown in FIG. 2, includes a data register 21 to which the digital data RGB is inputted from the timing controller 1; a shift register 22 for generating a sampling clock; a first latch 23, a second latch 24, a digital/analog converter (hereinafter, referred to as “DAC”) and an output circuit 26 which are connected between the shift register 22, and k (with ‘k’ being an integer less than ‘m’) number of data lines DL1 to DLk; and a gamma voltage supplier 27.
The data register 21 supplies the digital data RGB from the timing controller 1 to the first latch 23. The shift register 22 shifts the source start pulse SSP from the timing controller 1 in accordance with the source sampling clock signal SSC to generate the sampling signal. Further, the shift register 22 shifts the source start pulse SSP to transmit a carry signal CAR from the shift register 22 to the next step of the IC 3A. The first latch 23 sequentially samples the digital data RGB received from the data register 21 in response to the sampling signal which is sequentially inputted from the shift register 22. The second latch 24 latches the data inputted from the first latch 23, and then simultaneously outputs the latched data in response to the source output enable signal SOE received from the timing controller 1. The DAC 25 converts the data from the second latch 24 and the gamma voltages DGH, DGL from the gamma voltage supplier 27. The gamma voltages DGH, DGL are analog voltages which correspond to each of two gray levels of the digital input data. The output circuit 26 includes an output buffer connected to each of the data lines. The gamma voltage supplier 27 subdivides a gamma reference voltage to supply the gamma voltage corresponding to each gray level to the DAC 25.
The data IC 3A incurs an increased load and an increased driving frequency as the liquid crystal display device is configured to be of a relatively larger size and to have a substantially high precision, thereby increasing a generated heat. Due to the generated heat of the data IC 3A, the driving reliability of the data IC 3A is decreased and the operable safety may be dangerously compromised, e.g., a fire may occur. A substantial contributing source for generating heat in the data IC 3A is an output buffer 26A, shown in FIG. 3. That is, the data IC 3A generates heat by the power consumption due to currents Isource, and iSINK flowing through corresponding internal resistant components of the output buffer 26A.
In order to improve a charge characteristic of the liquid crystal cell and to reduce power consumption, the data IC is trendily operably configured using a charge share method or a pre-charge method. In the charge share method, the data voltage is supplied to each data line while the data lines are separated after connecting the adjacent data lines and pre-charging the data line with a charge voltage which is generated due to a charge share between the data lines. In the pre-charge method, the data voltage is supplied to the data line after pre-charging the data line with the pre-charge voltage which is a pre-set external voltage.
In the charge share method, as shown in FIG. 4, a relatively large amount of current flows in the output buffer 26A, namely in an output buffer driving section, when the charge share voltage Vshare is changed or switched to the data voltage, thereby substantially increasing the generated heat and power consumption. In the pre-charge method, as shown in FIG. 5, the voltage of a driving area of the output buffer 26A is reduced, to lower the temperature of the data IC 3A, to the pre-charge voltages +Vpre and −Vpre supplied from a white or grid voltage of a relatively high external voltage initially provided to the data IC 3A when the data voltage is relatively higher. However, the temperature of the data IC 3A is increased and its power consumption is rapidly increased in the pre-charge driving area 51, 52 of a low data voltage due to the pre-charge voltages +Vpre, and −Vpre, which are supplied from the relatively high external voltage, in a data voltage which is below a middle point of the high external voltage.